View QL4058_718739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2002 quicklogic corporation www.quicklogic.com 1 ? ? device highlights high performance & high density 58,000 usable pld gates with 252 i/os 300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos 0.35 m four-layer metal non-volatile cmos process for smallest die sizes high speed embedded sram 18 dual-port ram modules, organized in user-configurable 1,152 bit blocks 5 ns access times, each port independently accessible fast and efficient for fifo, ram, and rom functions easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with both 3.3 v and 5.0 v devices pci compliant with 3.3 v and 5.0 v busses for -1/-2/-3/-4 speed grades full jtag boundary scan i/o cells with individually controlled registered input path and output enables figure 1: quickram block diagram 18 ra m blocks 1,008 hi gh s pee d logic cells interface QL4058 quickram data sheet 58,000 usable pld gate quickram esp combining performance, density and em bedded ram
2 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h architecture overview the quickram family of esps (embedded standard products) offers fpga logic in combination with dual-por t sram modules. the QL4058 is a 58,000 usable pld gate member of the quickram family of esps. quickram esps are fabricated on a 0.35 m four-layer metal process using quicklogic's patented vialink ? tm technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. the QL4058 contains 1,008 logic cells and 18 dual port ram modules (see figure 1 ). each ram module has 1,152 ram bits, for a total of 20,736 bits. ram modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) 18 (wide), 128 9, 256 4, or 512 2 (see figure 4 ). with a maximum of 252 i/os, the QL4058 is available in 208-pqfp, 240-pin pqfp, and 456-pin pbga packages. designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see figure 2 ). this approach allows up to 512-deep configurations as large as 16 bits wide in the smallest quickram device and 44 bits wide in the largest device. software support for the complete quickram family, including the QL4058, is available through two basic packages. the turnkey quickworks ? tm package provides the most complete esp software solution from design entry to logic synthesis, to place and route, to simulation. the quicktools package provides a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, aldec, or other third-party tools for design entry, synthesis, or simulation. the quicklogic ? tm variable grain logic cell features up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. each cell has a fan- in of 29 including register and control lines (see figure 3 ). figure 2: quickram module bits rdata wdata raddr rdata waddr wdata ram module (1,152 bits) ram module (1,152 bits)
? 2002 quicklogic corporation www.quicklogic.com 3 QL4058 quickram data sheet rev h product summary total of 252 i/o pins 244 bi-directional input/output pins, pci- compliant for 5.0 v and 3.3 v buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins eight low-skew distributed networks two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs?each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock, set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control?each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance silicon input + logic cell + output total delays = under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz fifo speeds over 160+ mhz
4 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h
? 2002 quicklogic corporation www.quicklogic.com 5 QL4058 quickram data sheet rev h electrical specifications ac characteristics at v cc = 3.3 v, ta = 25 c (k = 1.00) to calculate delays, multiply the appropriate k factor from table 10: operating range by the following numbers in the tables provided. figure 3: quickram logic cell table 1: logic cell symbol parameter propagation delays (ns) fanout (5) 1 2 3 4 5 t pd combinatorial delay a a. these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. 1.4 1.7 1.9 2.2 3.2 t su setup time a 1.7 1.7 1.7 1.7 1.7 t h hold time 0.0 0.0 0.0 0.0 0.0 t clk clock to q delay 0.7 1.0 1.2 1.5 2.5 t cwhi clock high time 1.2 1.2 1.2 1.2 1.2 t cwlo clock low time 1.2 1.2 1.2 1.2 1.2 t set set delay 1.0 1.3 1.5 1.8 2.8 t reset reset delay 0.8 1.1 1.3 1.6 2.6 t sw set width 1.9 1.9 1.9 1.9 1.9 t rw reset width 1.8 1.8 1.8 1.8 1.8 qs a1 a2 a3 a4 a5 a6 f1 f2 f3 f4 f5 f6 qs op b1 b2 c1 c2 mp ms d1 d2 e1 e2 np ns qc qr oz az qz nz fz
6 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h figure 4: quickram module table 2: ram cell synchronous write timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 t swa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 t swd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 t swe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 t hwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 t wcrd wclk to rd (wa=ra) a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 5.0 5.3 5.6 5.9 7.1 table 3: ram cell synchronous read timing symbol parameter propagation delays (ns) fanout logic cells 1 2 3 4 5 t sra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 t hra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 t sre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 t hre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 t rcrd rclk to rd a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 4.0 4.3 4.6 4.9 6.1 wa wd we wclk re rclk ra rd [8:0] [17:0] [8:0] [17:0] mode asyncrd [1:0]
? 2002 quicklogic corporation www.quicklogic.com 7 QL4058 quickram data sheet rev h table 4: ram cell asynchronous read timing symbol parameter propagation delays (ns) fanout 1 2 3 4 5 rpdrd ra to rd a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 3.0 3.3 3.6 3.9 5.1 table 5: input-only / clock cells symbol parameter propagation delays (ns) fanout 1 2 3 4 8 12 24 t in high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 t ini high drive input, inverting delay 1.6 1.7 .19 2.0 2.5 3.0 4.5 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 t iclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 t irst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 t iesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 table 6: clock cells symbol parameter propagation delays (ns) fanout a a. the array distributed networks consist of 40 half columns and the global distributed networks con- sist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to eight loads per half column. the global clock has up to 11 loads per half column. 1 2 3 4 8 10 11 t ack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 t gckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 t gckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
8 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h figure 5: loads used for t pxz table 7: i/o cell input delays symbol parameter propagation delays (ns) fanout a a. stated timing for worst case propagation delay over process variation at v cc = 3.3 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. 1 2 3 4 8 10 t i/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 t isu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 t ih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 t ioclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 t iorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 t iesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 t ieh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 table 8: i/o cell output delays symbol parameter propagation delays (ns) output load capacitance (pf) 3 50 75 100 150 t outlh output delay low to high 2.1 2.5 3.1 3.6 4.7 t outhl output delay high to low 2.2 2.6 3.2 3.7 4.8 t pzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 t pzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 t phz output delay high to tri-state a a. these loads are used for t pxz (see figure 5 ) 2.0 - - - - t plz output delay high to tri-state a 1.2 - - - - 1? 1? tphz tplz 5 pf 5 pf
? 2002 quicklogic corporation www.quicklogic.com 9 QL4058 quickram data sheet rev h dc characteristics the dc specifications are provided in the tables below. table 9: absolute maximum ratings parameter value parameter value v cc voltage -0.5 v to 4.6 v dc input current 20 ma v ccio voltag e -0.5 v to 7.0 v esd pad protection 2000 v input voltage -0.5 v to v ccio +0.5 v storage temperature -65c to +150c latch-up immunity 200 ma lead temperature 300c table 10: operating range symbol parameter military industrial commercial unit min max min max min max v cc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v v ccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 - -40 85 0 70 c tc case temperature - 125 - - - - c k delay factor -0 speed grade 0.42 2.03 0.43 1.90 0.46 1.85 n/a -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 n/a -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 n/a -3 speed grade 0.43 0.90 0.46 0.88 n/a -4 speed grade 0.43 0.82 0.46 0.80 n/a
10 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h table 11: dc characteristics symbol parameter conditions min max units vih input high voltage 0.5 v cc v ccio + 0.5 v vil input low voltage -0.5 0.3 v cc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma a a. applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. 0.45 v iol = 1.5 ma 0.1 v cc v ii i or i/o input leakage current vi = v ccio or gnd -10 10 a ioz 3-state output leakage current vi = v ccio or gnd -10 10 a ci input capacitance b b. capacitance is sample tested only. clock pins are 12 pf maximum. 10 pf ios output short circuit current c c. only one output at a time. duration should not exceed 30 seconds. vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current d d. for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade devices and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer applications group (see contact information ) vi, vio = v ccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 a
? 2002 quicklogic corporation www.quicklogic.com 11 QL4058 quickram data sheet rev h kv and kt graphs figure 6: voltage factor vs. supply voltage figure 7: temperature factor vs. operating temperature 0.9200 0.9400 0.9600 0.9800 1.0000 1.0200 1.0400 1.0600 1.0800 1.1000 3 3.1 3.2 3.3 3.4 3.5 3.6 voltage factor vs. supply voltage supply voltage (v) kv 0.85 0.90 0.95 1.00 1.05 1.10 1.15 -60 -40 -20 0 20 40 60 80 temperature factor vs. operating temperature junction temperature c kt
12 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h power-up sequencing figure 8: power-up requirements the following requirements must be met when powering up the device (see figure 8 ): when ramping up the power supplies keep (v ccio -v cc ) max 500 mv. deviation from this recommendation can cause permanent damage to the device. v ccio must lead v cc when ramping the device. the power supply must take greater than or equal to 400 s to reach vcc. ramping to v cc /v ccio earlier than 400 s can cause the device to behave improperly. an internal diode is present in-between v cc and v ccio , as shown in figure 9 . figure 9: internal diode between vcc and vccio voltage v ccio v cc (v ccio -v cc ) max time 400 us v cc v cc v ccio internal logic cells, ram blocks, etc io cells
? 2002 quicklogic corporation www.quicklogic.com 13 QL4058 quickram data sheet rev h jtag figure 10: jtag block diagram microprocessors and application specific inte grated circuits (asics) pose many design challenges. one of these challenges concerns the accessibility of test points. the joint test access group (jtag) formed in response to this challenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir); these allow users to run three required tests, along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
14 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h the jtag 1149.1 standard require s the following three tests: extest instruction. the extest instruction performs a pcb interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap's test data in (tdi) and test data out (tdo) pins. boundary scan cells are preloaded with test patterns (via the sample/preload instruction), and input boundary cells capture the input data for analysis. sample/preload instruction. this instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed via a data scan operation, allowing users to samp le the functional data entering and leaving the device. bypass instruction. the bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. the bypass instruction allows users to test a device without passing through other devices. the bypass register connects the tdi and tdo pins, allowing serial data to be transferred through a device without affecting the operation of the device.
? 2002 quicklogic corporation www.quicklogic.com 15 QL4058 quickram data sheet rev h pin descriptions ordering information table 12: pin descriptions pin function description tdi/rsi test data in for jtag /ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to v cc if unused. trstb/rro active low reset for jtag /ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to v cc or ground if not used for jtag. tdo/rco test data out for jtag /ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3 v supply. vccio input voltage tolerance pin connect to 5.0 v supply if 5 v input tolerance is required, otherwise connect to 3.3 v supply. gnd ground pin connect to ground. gnd/therm ground/thermal pin available on 456-pbga only. connect to ground plane on pcb if heat sinking desired. otherwise may be left unconnected. ql 4058 - 1 pq208 c quicklogic device quickram device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow operating range c = commercial i = industrial m = military package code pq208 = 208-pin pqfp pq240 = 240-pin pqfp pb456 = 456-pin pbga * contact quicklogic regarding availabliity
16 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h 208 and 240 pqfp pinout diagrams figure 11: top view of 208 pin pqfp figure 12: top view of 240 pin pqfp pin 1 pin 53 pin 105 pin 157 QL4058-1pq208c quickram pin 1 pin 61 pin 121 pin 181 QL4058-1pq240c quickram
? 2002 quicklogic corporation www.quicklogic.com 17 QL4058 quickram data sheet rev h 208 and 240 pqfp pinout table table 13: 208/240 pqfp pinout table 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 1208 i/o 51 43 gnd 98 84 i/o 145 125 i/o 194 168 i/o 2 1 i/o 52 44 i/o 99 85 i/o 146 126 i/o 195 169 i/o 32 i/o 53 45 i/o 100 86 i/o 147 127 gnd 196 nc i/o 4 3 i/o 54 46 i/o 101 87 i/o 148 128 i/o 197 170 i/o 54 i/o 55 47 i/o 102 88 i/o 149 nc i/o 198 171 i/o 6 5 i/o 56 48 i/o 103 89 i/o 150 129 glck/i 199 172 i/o 7nc i/o 57 nc i/o 104 90 i/o 151 130 aclk/i 200 173 i/o 8 6 i/o 58 49 i/o 105 91 i/o 152 131 vcc 201 174 i/o 97 i/o 59 50 i/o 106 92 i/o 153 132 glck/i 202 175 i/o 10 8 i/o 60 51 i/o 107 nc i/o 154 133 glck/i 203 nc i/o 11 9 i/o nc 52 i/o 108 93 i/o 155 134 vcc 204 176 i/o 12 10 vcc nc 53 i/o 109 94 i/o 156 135 i/o 205 177 gnd 13 11 i/o 61 54 tdi 110 95 gnd 157 136 i/o 206 178 i/o 14 12 gnd 62 nc i/o nc 96 i/o 158 nc i/o 207 179 i/o 15 13 i/o 63 nc i/o 111 97 vcc 159 137 i/o 208 nc i/o 16 14 i/o 64 55 i/o nc 98 i/o 160 nc gnd 209 180 i/o 17 nc i/o 65 56 i/o nc 99 i/o 161 138 i/o 210 181 i/o 18 15 i/o 66 nc i/o 112 100 i/o 162 139 i/o 211 182 gnd 19 16 i/o 67 57 i/o 113 nc i/o 163 140 i/o 212 nc vcc 20 17 i/o 68 58 i/o 114 101 i/o 164 141 i/o 213 183 i/o 21 18 i/o 69 59 gnd 115 nc i/o 165 142 i/o 214 184 i/o 22 19 i/o 70 60 i/o 116 102 i/o 166 nc i/o 215 185 i/o 23 20 i/o 71 61 vcc 117 nc i/o 167 143 i/o 216 186 i/o 24 nc i/o 72 62 i/o 118 nc i/o 168 144 i/o 217 187 vccio 25 21 i/o 73 63 i/o 119 103 trstb 169 145 vcc 218 188 i/o 26 22 i/o 74 64 i/o 120 104 tms 170 nc i/o 219 nc i/o 27 23 gnd 75 nc i/o 121 105 i/o 171 146 i/o 220 189 i/o 28 24 i/o 76 65 i/o 122 nc i/o 172 147 gnd 221 190 i/o 29 25 gclk/i 77 66 i/o 123 106 i/o 173 148 i/o 222 191 i/o 30 26 aclk/i 78 67 i/o 124 107 i/o 174 149 i/o 223 192 i/o 31 27 vcc 79 nc i/o 125 108 i/o 175 150 i/o 224 193 i/o 32 28 gclk/i 80 68 i/o 126 109 i/o 176 151 i/o 225 194 i/o 33 29 gclk/i 81 69 i/o 127 nc i/o 177 152 i/o 226 nc i/o 34 30 vcc 82 70 i/o 128 110 i/o 178 153 i/o 227 195 i/o 35 31 i/o 83 nc i/o 129 111 i/o 179 154 i/o 228 196 i/o 36 32 i/o nc 71 i/o 130 112 i/o 180 155 i/o 229 197 i/o 37 nc gnd 84 nc i/o 131 113 i/o nc 156 i/o 230 198 i/o 38 33 i/o 85 72 i/o 132 114 vcc 181 157 tck 231 nc i/o 39 nc i/o 86 73 gnd 133 115 i/o 182 158 stm 232 199 gnd 40 34 i/o 87 74 i/o 134 116 gnd 183 nc i/o 233 200 i/o 41 35 i/o 88 nc vcc 135 117 i/o 184 159 i/o 234 201 vcc 42 36 i/o 89 75 i/o 136 nc i/o 185 160 i/o 235 202 i/o 43 nc i/o 90 76 i/o 137 118 i/o 186 161 i/o 236 203 i/o 44 37 i/o 91 77 i/o 138 119 i/o 187 162 i/o 237 204 i/o 45 38 i/o 92 78 gnd 139 120 i/o 188 163 gnd 238 205 i/o 46 39 i/o 93 79 i/o 140 121 i/o 189 164 i/o 239 206 i/o 47 nc i/o 94 80 i/o 141 nc i/o 190 165 vcc 240 207 tdo 48 40 i/o 95 81 i/o 142 122 i/o 191 166 i/o 49 41 vcc 96 82 i/o 143 123 i/o 192 nc i/o 50 42 i/o 97 83 vccio 144 124 i/o 193 167 i/o
18 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h 208 and 240 pqfp mechanical drawing figure 13: 208 pqfp mechanical drawing
? 2002 quicklogic corporation www.quicklogic.com 19 QL4058 quickram data sheet rev h 456 pbga pinout diagram figure 14: 456 pbga pinout diagram QL4058-1pb456c quickram bottom view top view pin a1 corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
20 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h 456 pbga pinout table table 14: 456 pbga pinout table 456 function 456 function 456 function 456 function 456 function a1 i/o c1 i/o e1 i/o h23 nc m23 nc a2 i/o c2 i/o e2 i/o h24 i/o m24 i/o a3 i/o c3 i/o e3 i/o h25 nc m25 i/o a4 i/o c4 tdo e4 i/o h26 i/o m26 i/o a5 i/o c5 i/o e5 gnd j1 i/o n1 gclk/i a6 i/o c6 i/o e6 vcc j2 i/o n2 i/o a7 i/o c7 i/o e7 gnd j3 i/o n3 i/o a8 i/o c8 i/o e8 nc j4 nc n4 gclk/i a9 nc c9 i/o e9 gnd j5 gnd n5 vcc a10 i/o c10 i/o e10 i/o j22 nc n11 gnd/therm a11 i/o c11 i/o e11 gnd j23 nc n12 gnd/therm a12 vccio c12 i/o e12 gnd j24 i/o n13 gnd/therm a13 i/o c13 i/o e13 vcc j25 i/o n14 gnd/therm a14 i/o c14 i/o e14 gnd j26 i/o n15 gnd/therm a15 nc c15 i/o e15 gnd k1 nc n16 gnd/therm a16 i/o c16 i/o e16 gnd k2 nc n22 gnd a17 nc c17 nc e17 nc k3 i/o n23 i/o a18 i/o c18 nc e18 gnd k4 i/o n24 i/o a19 i/o c19 i/o e19 nc k5 vcc n25 nc a20 i/o c20 i/o e20 gnd k22 gnd n26 i/o a21 nc c21 i/o e21 vcc k23 i/o p1 i/o a22 i/o c22 i/o e22 gnd k24 i/o p2 i/o a23 nc c23 i/o e23 i/o k25 nc p3 nc a24 i/o c24 i/o e24 i/o k26 i/o p4 i/o a25 i/o c25 tck e25 i/o l1 i/o p5 nc a26 i/o c26 nc e26 i/o l2 i/o p11 gnd/therm b1 i/o d1 i/o f1 i/o l3 i/o p12 gnd/therm b2 nc d2 i/o f2 i/o l4 i/o p13 gnd/therm b3 i/o d3 i/o f3 nc l5 nc p14 gnd/therm b4 nc d4 gnd f4 nc l11 gnd/therm p15 gnd/therm b5 nc d5 nc f5 vcc l12 gnd/therm p16 gnd/therm b6 nc d6 nc f22 vcc l13 gnd/therm p22 nc b7 nc d7 i/o f23 nc l14 gnd/therm p23 gclk / i b8 nc d8 i/o f24 i/o l15 gnd/therm p24 gclk / i b9 i/o d9 gnd f25 i/o l16 gnd/therm p25 nc b10 nc d10 i/o f26 i/o l22 nc p26 aclk / i b11 nc d11 i/o g1 i/o l23 i/o r1 nc b12 i/o d12 gnd g2 i/o l24 i/o r2 i/o b13 i/o d13 i/o g3 i/o l25 nc r3 i/o b14 nc d14 i/o g4 i/o l26 i/o r4 nc b15 i/o d15 gnd g5 nc m1 aclk / i r5 nc b16 i/o d16 i/o g22 gnd m2 gclk/i r11 gnd/therm b17 i/o d17 i/o g23 nc m3 i/o r12 gnd/therm b18 i/o d18 gnd g24 i/o m4 nc r13 gnd/therm b19 i/o d19 i/o g25 i/o m5 gnd r14 gnd/therm b20 i/o d20 nc g26 i/o m11 gnd/therm r15 gnd/therm b21 i/o d21 nc h1 nc m12 gnd/therm r16 gnd/therm b22 i/o d22 i/o h2 i/o m13 gnd/therm r22 vcc b23 nc d23 gnd h3 nc m14 gnd/therm r23 nc b24 i/o d24 i/o h4 i/o m15 gnd/therm r24 nc b25 i/o d25 i/o h5 nc m16 gnd/therm r25 i/o b26 stm d26 i/o h22 nc m22 nc r26 gclk / i (sheet 1 of 2)
? 2002 quicklogic corporation www.quicklogic.com 21 QL4058 quickram data sheet rev h t1 i/o w5 nc ab15 vcc ad3 i/o ae17 i/o t2 i/o w22 nc ab16 i/o ad4 i/o ae18 i/o t3 i/o w23 i/o ab17 nc ad5 i/o ae19 i/o t4 i/o w24 i/o ab18 vcc ad6 i/o ae20 i/o t5 vcc w25 i/o ab19 gnd ad7 i/o ae21 i/o t11 gnd/therm w26 nc ab20 nc ad8 i/o ae22 nc t12 gnd/therm y1 nc ab21 vcc ad9 nc ae23 nc t13 gnd/therm y2 i/o ab22 gnd ad10 i/o ae24 tms t14 gnd/therm y3 nc ab23 i/o ad11 nc ae25 i/o t15 gnd/therm y4 i/o ab24 nc ad12 i/o ae26 i/o t16 gnd/therm y5 i/o ab25 i/o ad13 i/o af1 i/o t22 gnd y22 gnd ab26 i/o ad14 i/o af2 nc t23 i/o y23 i/o ac1 i/o ad15 i/o af3 i/o t24 i/o y24 nc ac2 i/o ad16 i/o af4 nc t25 nc y25 i/o ac3 nc ad17 i/o af5 i/o t26 i/o y26 i/o ac4 gnd ad18 i/o af6 i/o u1 nc aa1 i/o ac5 nc ad19 nc af7 i/o u2 i/o aa2 i/o ac6 nc ad20 nc af8 i/o u3 i/o aa3 nc ac7 nc ad21 i/o af9 i/o u4 i/o aa4 nc ac8 nc ad22 i/o af10 i/o u5 gnd aa5 vcc ac9 nc ad23 trstb af11 nc u22 nc aa22 vcc ac10 nc ad24 nc af12 i/o u23 i/o aa23 nc ac11 i/o ad25 i/o af13 i/o u24 i/o aa24 i/o ac12 nc ad26 i/o af14 nc u25 i/o aa25 i/o ac13 i/o ae1 tdi af15 nc u26 i/o aa26 i/o ac14 vccio ae2 i/o af16 i/o v1 i/o ab1 nc ac15 nc ae3 i/o af17 i/o v2 i/o ab2 i/o ac16 nc ae4 i/o af18 i/o v3 nc ab3 i/o ac17 nc ae5 i/o af19 nc v4 nc ab4 i/o ac18 nc ae6 i/o af20 i/o v5 nc ab5 gnd ac19 i/o ae7 i/o af21 i/o v22 gnd ab6 vcc ac20 i/o ae8 i/o af22 i/o v23 nc ab7 nc ac21 i/o ae9 i/o af23 i/o v24 i/o ab8 nc ac22 nc ae10 i/o af24 i/o v25 nc ab9 nc ac23 gnd ae11 i/o af25 i/o v26 i/o ab10 vcc ac24 nc ae12 i/o af26 i/o w1 i/o ab11 gnd ac25 i/o ae13 i/o w2 i/o ab12 nc ac26 i/o ae14 i/o w3 i/o ab13 i/o ad1 i/o ae15 i/o w4 i/o ab14 gnd ad2 nc ae16 i/o table 14: 456 pbga pinout table (continued) 456 function 456 function 456 function 456 function 456 function (sheet 2 of 2)
22 www.quicklogic.com ? 2002 quicklogic corporation QL4058 quickram data sheet rev h 456 pbga mechanical drawing figure 15: 456 pbga mechanical drawing
? 2002 quicklogic corporation www.quicklogic.com 23 QL4058 quickram data sheet rev h contact information telephone:408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ revision history copyright information copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this product brief, and the accompanying software programs are pro- tected by copyright. all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to make periodic modifications of this product without obligation to notify any per- son or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of quicklogic is prohib- ited. quicklogic, pasic, and vialink are registered trademarks, and spde and quick works are trade- marks of quicklogic corporation. verilog is a registered trademark of cadence design systems, inc. table 15: revision history revision date comments a not avail. first release. b not avail. c not avail. d not avail. e not avail. f not avail. g may 2000 update of ac/dc specs and reformat h may 2002 added kfactor, power-up, jtag and mechanical drawing information. reformatted.

▲Up To Search▲

Price & Availability of QL4058

	To Download QL4058 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .